1. Field of the Invention
The present invention relates to the fabrication of a microelectronic device such as a semiconductor integrated circuit, more particularly to the formation of tapered holes and other tapered features.
2. Description of the Related Art
The trend of semiconductor devices toward higher performance and smaller geometries creates a growing need to shrink the dimensions of their circuit patterns, including the diameters of contact holes and via holes. Reducing the diameters of these holes provides an increased mask alignment margin during the fabrication process, leading to increased fabrication yields, and contributes to the reduction of semiconductor chip size so that more chips can be fabricated on a single wafer, leading to reduced fabrication costs.
Tapered etching of contact and via holes is one known method of obtaining these benefits. Conventional tapered etching uses a resist pattern with vertical walls as an etching mask, but deposits material on the inner walls of the holes as they are etched, thereby gradually reducing the size of the holes. When applied to, for example, a wafer on which a hole resist pattern with vertical holes 0.26 micrometers (0.26 μm) in diameter has been formed by standard photolithography, this method can form holes that taper from a diameter of 0.26 μm at the top to 0.20 μm at the bottom. Descriptions of this method can be found in Japanese Unexamined Patent Application Publications No. 2000-182940, 2001-307993, 2001-326153, and 2001-332484.
In the tapered etching technology described above, however, it is difficult to control the taper angle, and etching may stop due to the deposition of material, leaving holes incompletely formed.